1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a semiconductor device having an improved construction in the interlayer insulating film in which a buried wiring is formed and a method of manufacturing the particular semiconductor device.
2. Description of the Related Art
In recent years, the delay in the signal transmission of the wiring included in a ULSI has come to form a problem in accordance with progress in the density of the ULSI. As a measure for overcoming the problem, efforts are being made in an attempt to decrease the dielectric constant of the interlayer insulating film and to lower the resistance of the wiring material. It is possible to decrease the dielectric constant of the interlayer insulating layer by using an insulating material having a low dielectric constant, e.g., having a relative dielectric constant lower than 2.5. On the other hand, the use of, for example, copper wiring has attracted attention as a measure for lowering the resistance of the wiring material.
The use of copper wiring is certainly advantageous for lowering the resistance of the wiring material. However, it is very difficult to apply a fine processing to the copper wiring. Such being the situation, a damascene method is employed in general for forming copper wiring. In the damascene method, a trench equal in width to the wiring is formed first in an interlayer insulating film formed on a semiconductor substrate, followed by burying a wiring material such as copper in the trench. Then, the excess wiring material is removed from the surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method so as to form a buried copper wiring.
Where an insulating material having a low mechanical strength and a low dielectric constant is used for forming the interlayer insulating film, it is required for the interlayer insulating film to exhibit a high resistance to the dry etching treatment (i.e., a high resistance to the plasma etching) and a high resistance to a CMP treatment. Under the circumstances, it is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-358218 that an insulating material layer having a larger mechanical strength is laminated as a cap layer on an insulating material layer having a low dielectric constant. To be more specific, a wiring trench is formed in an interlayer insulating film of a laminate structure consisting of an insulating film having a low dielectric constant and a cap insulating layer. Then, a wiring material is buried on the interlayer insulating film including the wiring trench, followed by applying a CMP treatment so as to form a buried wiring.
However, the lamination between the insulating film having a low dielectric constant and the cap insulating layer is accompanied by stress, with the result that peeling tends to take place at the interface between the insulating film having a low dielectric constant and the cap insulating film during the CMP treatment involving the application of a mechanical force. It follows that the reliability and the yield of the semiconductor device are reduced.
As pointed out above, in the conventional semiconductor device, it was possible for the interlayer insulating film of a laminate structure formed of an insulating film having a low dielectric constant to be peeled in forming a wiring by burying a wiring material in the interlayer insulating film. Therefore, in the semiconductor device in which the dielectric constant of the interlayer insulating film is lowered for improving the performance of the semiconductor device, it is of great importance to prevent the interlayer insulating film of a laminate structure from being peeled so as to improve the reliability and the yield of the semiconductor device.